Tag Archives: AMD unveils EPYC Milan-X processors with up to 768MB of L3 cache per socket

AMD unveils EPYC Milan-X processors with up to 768MB of L3 cache per socket AMD announced the first official details for the Milan-X chips – a modification of the EPYC Milan server processors with 3D-stacked L3 cache (dubbed 3D V-Cache), which can be up to 768 MB in size. That massive hunk of cache canContinue reading “AMD unveils EPYC Milan-X processors with up to 768MB of L3 cache per socket”